W9425G6EH-5【PDF 9/54 页】IC DDR-400 SDRAM 256MB 66TSSOPII

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W9425G6EH

7. FUNCTIONAL DESCRIPTION

7.1

Power Up Sequence

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

CLK

CLK

Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined

1) Apply V DD before or at the same time as V DDQ .

2) Apply V DDQ before or at the same time as V TT and V REF .

Start Clock and maintain stable condition for 200 μS (min.).

After stable power and clock, apply NOP and take CKE high.

Issue precharge command for all banks of the device.

Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.

Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.

(An additional 200 cycles(min) of clock are required for DLL Lock before any executable

command applied.)

Issue precharge command for all banks of the device.

Issue two or more Auto Refresh commands.

Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.

Command

PREA

t RP

EMRS

2 Clock min.

MRS

2 Clock min.

PREA

t RP

AREF

t RFC

AREF

t RFC

MRS

2 Clock min.

ANY

CMD

200 Clock min.

Inputs

maintain stable

for 200 μS min.

Enable DLL

DLL reset with A8 = High

Disable DLL reset with A8 = Low

Initialization sequence after power-up

Publication Release Date:Dec. 03, 2008

-9-

Revision A08

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